Multi-Site Collaboration in System on Chip Design and Validation: The Intel Experience
Ketan Paranjape
Intel Corporation
M/S JF3-218, 2111 NE 25th Avenue,
Hillsboro, OR 97123, USA
ketan.paranjape@intel.com
Abstract- As companies expand their infrastructure to multiple countries to make their presence felt in those markets, to benefit from the local knowledge and talent pool, and to take advantage of favorable economics, critical projects are partitioned and handled by these new sites. This creates problems with project partitioning, communication, decision-making and logistics. Organizations therefore need to put a solid framework in place to manage these projects. Teams must develop and follow cross-site project management and execution guidelines in order to be successful.
This talk will address these concerns in the context of Intel SoC’s by walking through the integrated circuit design flows, design methodologies and standards, challenges in design and validation and finally address project planning, partitioning and execution.